1. Field of the Invention
The present invention relates to flash EPROM cells and methods for their construction. More particularly, the current invention relates to reducing leakage during source erase of flash EPROM cells. More specifically, the present invention provides new process techniques that reduce source leakage during source erase of flash EPROM cells. The current invention also provides novel semiconductor devices with a differentially doped source region that reduces leakage during source erase.
2. Discussion of Related Art
Erasable programmable read-only memory (EPROM) is a form of non-volatile memory. Non-volatile memory devices retain information when power to the device is interrupted and thus are important in the design of wireless and portable electronic devices. Non-volatile storage choices range from mask read-only memory (ROM), ultraviolet EPROM (UV-EPROM), flash EPROM and electrically erasable EPROM (EEPROM).
EPROM devices typically lack the density of ROM disks but are more flexible since coded changes can be accommodated. EPROM devices offer the further advantage of rapid access since reading and writing to these types of devices is not delayed by the latency periods characteristic of ROM devices.
Flash EPROM offers some of the advantages of EEPROM with the lower cost of UV-EPROM. All forms of EPROM use electrical injection methods to program individual memory cells but differ in the method of memory cell erasure. Ultraviolet light irradiation is used to erase UV-EPROM memory cells. This method is non-selective and requires removal of memory cells from the system for erasure. EEPROM systems use Fowler-Nordheim tunneling to erase single cells which offers reprogramming flexibility, high density and convenience, since removal of memory cells from the device is not required for erasure.
Flash EPROM also uses Fowler-Nordheim tunneling for non-selective memory cell erasure. Thus, flash EPROM provides the convenience and high density of EEPROM with the low cost of conventional UV-EPROM. Therefore, flash EPROM has become the storage method of choice in many portable consumer devices such as cell phones and hand held personal computers.
Two different methods, which employ Fowler-Nordheim tunneling, are typically used to erase flash EPROM cells. In channel or substrate erase, a positive bias of about 10.0 V is applied to the substrate of the memory cell. Similarly, a negative bias of about -5.0 V is applied to the gate of the memory cell. Electron tunneling from the gate to the substrate then erases the memory cell. Channel erase requires source isolation by the triple well process, which is complicated and expensive.
Source erase is similar to substrate erase except that a positive bias of about 5.0 V is applied to the source of the memory cell while a negative bias of about -10.0 V is applied to the gate of the memory cell. Since source erase does not require source isolation by the triple well process it is simpler and less expensive to implement than channel erase.
However, a significant problem with source erase of flash EPROM cells is source diode leakage to the substrate during erasure. Source leakage lengthens the time required to erase a flash EPROM and degrades performance. Source diode leakage must be minimized to increase source erase speed.
Three different mechanisms contribute to source diode leakage during source erase. Thermal leakage, which is intrinsic to any diode, is small and independent of electric field. Avalanche multiplication is electric field dependent and can become very large if the cell is not optimized during fabrication.
Band to band tunneling leakage is a fundamental problem with source erase (C. Chang et al., Tech. Dig. IEDM, 714, 1987; H. Kume et al., Tech. Dig. IEDM, 560, 1987). Band to band leakage wastes power since some of the diode current is dissipated in the substrate during erasure. Furthermore, constant source voltage is difficult to maintain in the presence of this type of leakage, which places significant demand on the charge pump capacitor. Thus, the difficulties caused by band to band leakage in generating and maintaining the voltage required to erase the device are frequently the limiting factor in source erasing flash cells.
The contour of the junction profile at the source edge under the stacked gate edge in flash EPROM cells strongly influences band to band tunneling. This may be best understood with reference to a prior art process typically used in the fabrication of flash EPROM cells, which is depicted in FIGS. 1-3.
FIG. 1 illustrates a partially fabricated semiconductor device 100 after stack etch. A pair of stacked gates 112 are disposed on a semiconductor substrate 102. Stacked gates 112 are comprised of a tunnel oxide layer 104, a first polysilicon layer 106, an ONO layer 108 and a second polysilicon layer 110. The partially fabricated semiconductor device 100 can be made by conventional methods known to one of skill in the semiconductor arts.
FIG. 2A illustrates the partially fabricated semiconductor device of FIG. 1 after masking, self-aligned source (SAS) etch and mask removal (Tang et al., U.S. Pat. No. 5,120,671). These processing steps are conventional and are well known to one of skill in the semiconductor arts.
SAS etch connects source regions between adjacent cells after stacked gate formation. More specifically, SAS etch etches field oxide regions, which are used to isolate the active regions of flash EPROM cells. Consequently, the source region, formed between field oxide regions of adjacent memory cells, is self-aligned with both the polysilicon word line and the field oxide region. Self-alignment of the source region with the polysilicon word line and the field oxide region increases the density and reduces the cell size of a memory cell. Thus, SAS etch increases the performance and cost-effectiveness of flash EPROM cells.
A significant problem with SAS etch is over etching of the semiconductor substrate 102 at region 116. Note that region 116 of the semiconductor substrate 102, which was exposed to SAS etch, is not level with the stacked gate edge. Contrastingly, regions 115 of the semiconductor substrate which were not exposed to SAS etch are level with the stacked gate edge.
More importantly, the SAS etch creates a gouge in the semiconductor substrate at regions 118 in FIG. 2A, which underlie the edge of stacked gates 112. Furthermore, the integrity of tunnel oxide layer 104 is affected since the stacked gate edge is exposed to the SAS etch conditions. FIG. 2B is an enlarged view of region 118, which illustrates the damage caused by SAS etch. Note that a portion of tunnel oxide layer 104 is etched under layer 106. The undercutting of semiconductor substrate 102 relative to the stacked gate edge 120 significantly damages the tunnel oxide layer 104. The ragged edge of the semiconductor substrate at 122 affects the uniformity of the subsequent ion implant to create the source region.
FIG. 3 illustrates the partially fabricated semiconductor device of FIG. 2 after SAS masking, source implantation, annealing and removal of the SAS mask. These conventional processing steps provide the source lines in a semiconductor device. Source region 124 has been formed under silicon surface 116. However, since the edge of the source region under the stacked gate 112 was damaged during SAS etch the implant is not uniform. The non-uniform implant in source region 124 leads to non-uniform erase in the flash memory array which is caused by an insufficient dopant dose in the source overlap region with the stacked gates 112. Furthermore, the non-uniform implant in source region 124 leads to excessive leakage caused by band to band tunneling, causing random failure in the array.
Nevertheless, it has become apparent that as flash EPROM cells shrink in size and increase in density that other methods of reducing source diode leakage are necessary. Thus, what is needed are efficient process methods that minimize band to band tunneling leakage caused by SAS etch.